Printed circuit board substrate

ABSTRACT

A printed circuit board substrate includes a metal-clad substrate and a number of N spaced circuit substrates arranged on the metal-clad substrate along an imaginary circle, and N is a natural number greater than 2. The circuit substrates are equiangularly arranged about the center of the circle, and each of the circuit substrates is oriented 360/N degrees with respect to a neighboring printed circuit board.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional application of patent application Ser.No. 12/332,321 filed on Dec. 10, 2008 from which it claims the benefitof priority under 35 U.S.C. 120. The patent application Ser. No.12/332,321 in turn claims the benefit of priority under 35 U.S.C. 119from Chinese Patent Application 200810301211.3, filed on Oct. 22, 2009.

BACKGROUND

1. Technical Field

The present disclosure relates to printed circuit boards, particularlyto a printed circuit board substrate.

2. Description of Related Art

Rigid-flexible printed circuit boards (R-F PCBs) are widely used inelectronic devices. A rigid-flexible printed circuit board has a rigidregion and a flexible region. The rigid region is configured forassembling electronic components and maintaining electrical connectionsamong the electronic components. The flexible region is connected to therigid region and can be bent relative to the rigid region. Thus, therigid-flexible printed circuit board can be assembled with a number ofelectronic components, and occupies little space by bending the flexibleregion.

A typical method for manufacturing a batch of rigid-flexible printedcircuit board is shown in FIGS. 13-17. As shown in FIG. 13 and FIG. 14,a rigid-flexible printed circuit board substrate 30 includes a rigidsubstrate 31 and three flexible substrates 32 laminated thereon. Therigid substrate 31 includes a resin layer 311 and a copper layer 312configured to form predetermined electrically conductive patterns on theresin layer 311. The rigid-flexible printed circuit board substrate 30defines three processing regions 310, each of corresponds to a flexiblesubstrate 32. Each of the flexible substrates 32 includes an insulationlayer 321 and a plurality of electrical traces 322 formed thereon. Asshown in FIG. 15 and FIG. 16, a photolithographic process is performedto make a predetermined electrically conductive pattern from the copperlayer 312 on the resin layer 311.

The photolithographic process is described in detail as following.Firstly, referring to FIG. 15, a photoresist layer 40 is applied on thecopper layer 312 and covers the three processing regions 310. Secondly,the photoresist layer 40 is exposed by UV-light passing through a photomask 50. The photo mask 50 has three exposing sections 51, each of whichhas patterned openings 510 defined therein. Thirdly, referring to FIG.16, the photoresist layer 40 is developed, the copper layer 312 isetched to form predetermined electrically conductive patterns 312 a, andthe residual photoresist layer 40 is removed. After thephotolithographic process, plated through holes (not shown) are formedin the rigid-flexible printed circuit board substrate 30 to interconnectthe electrically conductive patterns 312 a and the electrical traces 322of the flexible substrates 32. Then the rigid-flexible printed circuitboard substrate 30 is cut along imaginary boundary lines between themanufacturing regions 310, and three rigid-flexible printed circuitboards 60 are obtained as shown in FIG. 17.

In the photolithographic process, the photo mask 50 should be preciselyaligned with the rigid substrate 31 when the photoresist layer 40 isexposed because the electrical traces 322 of the flexible circuit board32 should correspond to the electrically conductive patterns 312 a ofthe rigid substrate 31. If the photo mask 50 deviates from desiredposition, the electrical conductive patterns 312 a would not align withthe electrical traces 322 and could not be electrically connected to theelectrical traces 322 by plated through holes, thereby quality of thebatch of rigid-flexible printed circuit boards 60 is affected.

What is needed, therefore, is a printed circuit board substrate whichcan overcome the above-described problems.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present embodiments can be better understood withreference to the following drawings. The components in the drawings arenot necessarily drawn to scale, the emphasis instead being placed uponclearly illustrating the principles of the present embodiments.Moreover, in the drawings, like reference numerals designatecorresponding parts throughout the several views.

FIG. 1 is a top view of a printed circuit board substrate, the printedcircuit board substrate includes four circuit substrates.

FIG. 2 is a sectional view of the printed circuit board substrate alongline II-II of FIG. 1, showing the printed circuit board substratefurther includes a first metal-clad substrate and a second metal-cladsubstrate.

FIG. 3 is a sectional view of the printed circuit board substrate alongline III-III of FIG. 1.

FIG. 4 is similar to FIG. 1, but showing four processing regions definedtherein.

FIG. 5 is similar to FIG. 4, but showing a photoresist layer applied onthe first metal-clad substrate of the printed circuit board substrate.

FIG. 6 is a sectional view of the printed circuit board substrate alongline VI-VI of FIG. 5.

FIG. 7 is a schematic view of a photo mask having a size matched withone processing region defined in the printed circuit board substrate.

FIG. 8A-8D are schematic views, showing a process for exposing thephotoresist layer.

FIG. 9 is similar to FIG. 5, but showing the photoresist layer beexposed completely.

FIG. 10 is similar to FIG. 9, but showing electrically conductivepatterns are formed in the first metal-clad substrate.

FIG. 11 is a sectional view of the printed circuit board substrate alongline XI-XI of FIG. 10.

FIG. 12 is a schematic view of four printed circuit boards, which areobtained by cutting the printed circuit board substrate of FIG. 10.

FIG. 13 is a schematic view of a typical rigid-flexible printed circuitboard substrate, the rigid-flexible printed circuit board substrateincluding a rigid substrate and three flexible substrates.

FIG. 14 is a sectional view of the rigid-flexible printed circuit boardsubstrate along line XIV-XIV of FIG. 13.

FIG. 15 is similar to FIG. 14, but showing a photoresist layer appliedon the rigid substrate is exposed by a photo mask and UV-light.

FIG. 16 is similar to FIG. 14, but showing electrically conductivepatterns are formed in the rigid substrate.

FIG. 17 is a sectional view of three rigid-flexible printed circuitboards, which are obtained by cutting the rigid-flexible printed circuitboard substrate shown in FIG. 16.

DETAILED DESCRIPTION

Embodiments will now be described in detail below with reference to thedrawings.

Referring to FIGS. 1-3, a printed circuit board substrate 100 includes afirst metal-clad substrate 110 a, a second metal-clad substrate 110 b,and four circuit substrates, i.e., a first circuit substrate 120 a, asecond circuit substrate 120 b, a third circuit substrate 120 c, and afourth circuit substrate 120 d.

The first metal-clad substrate 110 a includes a first insulation layer111 a and a first electrically conductive layer 112 a. The insulationlayer 111 a is configured for supporting the electrically conductivelayer 112 a. The electrically conductive layer 112 a is formed on theinsulation layer 111 a, and is fit to form electrically conductivepatterns in a subsequent process. The first substrate 110 a has arotation center denoted as O in the FIG. 1, and can coincide with itselfby rotating an angle less than 360 degrees about the rotation center O.In the illustrated embodiment, the first metal-clad substrate 110 a isin the shape of a square, and can regain an original orientation whenrotated 90 degrees, 180 degrees, or 270 degrees about the rotationcenter O.

The second metal-clad substrate 110 b has an identical structure as thefirst metal-clad substrate 110 a. The second metal-clad substrate 110 bincludes a second insulation layer 111 b opposite to the firstinsulation layer 111 a and a second electrically conductive layer 112 bformed on the insulation layer 111 b.

The first circuit substrate 120 a, the second circuit substrate 120 b,the third circuit substrate 120 c, and the fourth circuit substrate 120d have an identical structure. The first circuit substrate 120 a is adouble-sided copper clad laminate, and includes a first dielectric layer121 a, a plurality of first electrical traces 122 a (as an example,three parallel first electrical traces 122 a shown as dash lines inFIG. 1) and a plurality of second electrical traces 123 a. The firstelectrical traces 122 a are formed on a surface of the dielectric layer121 a, and the second electrical traces 123 a are formed on anothersurface of the dielectric layer 121 a opposite to the first electricaltraces 122 a. In the present embodiment, the first electrical traces 122a and the second electrical traces 123 a have the same patterns.Correspondingly, the second circuit substrate 120 b includes a seconddielectric layer 121 b, a plurality of third electrical traces 122 b,and a plurality of fourth electrical traces 123 b. The third circuitsubstrate 120 c includes a third dielectric layer 121 c, a plurality offifth electrical traces 122 c and a plurality of sixth electrical traces123 c. The fourth circuit substrate 120 d includes a fourth dielectriclayer 121 d, a plurality of seventh electrical traces 122 d and aplurality of eighth electrical traces 123 d.

The circuit substrates 120 a, 120 b, 120 c and 120 d are sandwichedbetween the first metal-clad substrate 110 a and the second metal-cladsubstrate 110 b. The first, third, fifth and seventh electrical traces122 a, 122 b, 122 c and 122 d are in intimate contact with the firstinsulation layer 111 a of the first metal-clad substrate 110 a. Thesecond, fourth, sixth and eighth electrical traces 123 a, 123 b, 123 c,and 123 d are in intimate contact with the second insulation layer 111 bof the second metal-clad substrate 110 b.

The circuit substrates 120 a, 120 b, 120 c, and 120 d are arranged alongan imaginary circle, and are equiangularly arranged about the center ofthe circle. In the illustrated embodiment, the four circuit substrates120 a, 120 b, 120 c, and 120 d are equiangularly arranged about therotation center O of the first metal-clad substrate 110 a. As such, thefour circuit substrates 120 a, 120 b, 120 c, and 120 d are arrangedcentrosymmetric with respect to the rotation center O of the firstmetal-clad substrate 110 a.

Additionally, each of the four circuit substrates 120 a, 120 b, 120 c,and 120 d is oriented at an angle of 90 degrees with respect to aneighboring circuit substrate. The first circuit substrate 120 a isoriented at an angle of 90 degrees with respect to the second circuitsubstrate 120 b, the second circuit substrate 120 b is oriented at anangle 90 degrees with respect to the third circuit substrate 120 c, thethird circuit substrate 120 c is oriented at an angle of 90 degrees withrespect to the fourth circuit substrate 120 d, and the fourth circuitsubstrate 120 d is oriented at an angle of 90 degrees with respect tothe first circuit substrate 120 a. Thus, the first circuit substrate 120a can coincide with the second circuit substrate 120 b by rotating 90degrees about the rotation center O of the first metal-clad substrate110 a, can coincide with the third circuit substrate 120 c by rotating180 degrees about the rotation center O, and can coincide with thefourth circuit substrate 120 d by rotating 270 degrees about therotation center O.

It is noted that the second metal-clad substrate 110 b may not benecessary in the printed circuit board substrate 100. That is, theprinted circuit board substrate 100 may only include the firstmetal-clad substrate 110 a and the four circuit substrates 120 a, 120 b,120 c and 120 d.

It is also noted that the number of the circuit substrates is notlimited to be four, less or more may be included in the printed circuitboard substrate 100 according to practical need. Denoting the number ofthe circuit substrates as N, N representing a natural number greaterthan 2, the circuit substrates should be arranged on the firstmetal-clad substrate 110 a along an imaginary circle, equiangularlyarranged about the center of the circle, and each of the circuitsubstrates should be oriented 360/N degrees with respect to aneighboring circuit substrate.

The metal-clad substrates 110 a, 110 b, and the circuit substrates 120a, 120 b, 120 c and 120 d each can be a rigid substrate or a flexiblesubstrate, thus the printed circuit board substrate 100 can be a rigid,flexible, or rigid-flexible substrate for manufacturing a batch ofrigid, flexible, or rigid-flexible printed circuit boards respectively.

A method for manufacturing a batch of printed circuit board according toan embodiment will now be described in detail.

The method includes the following steps in no particular order:

-   -   (1) providing a printed circuit board substrate including a        metal-clad substrate and multiple spaced circuit substrates,        {M_(i)}, i=1, 2, . . . , N, N being an integer greater than 2,        the circuit substrates, {M_(i)}, mounted on the metal-clad        substrate along an imaginary circle, the circuit substrates        being equiangularly arranged about the center of the circle, the        i+1th circuit substrate, M_(i+1), being oriented 360/N degrees        with respect to the ith neighboring circuit substrate, M_(i);    -   (2) defining multiple processing regions, {K_(i)}, i=1, 2, . . .        , N, N being an integer greater than 2, on the metal-clad        substrate, the processing regions, {K_(i)}, spatially        corresponding to the respective circuit substrates, {M_(i)};    -   (3) forming a photoresist layer on an opposite side of the        metal-clad substrate to the circuit substrates, the photoresist        layer including multiple photoresist layer sections, {P_(i)},        i=1, 2, . . . , N, N being an integer greater than 2, the        photoresist layer sections, {P_(i)}, respectively located at the        processing regions, {K_(i)};    -   (4) exposing the ith photoresist layer section, P_(i), which        spatially corresponds to the ith circuit substrate, M_(i);    -   (5) rotating the printed circuit board substrate an angle of        360/N degrees about the center of the circle;    -   (6) exposing the i+1th photoresist layer section, P_(i+1), which        is proximate to the ith photoresist layer section, P, and        spatially corresponds to the i+1th circuit substrate, M_(i+1);    -   (7) developing the ith photoresist layer section, P_(i);    -   (8) etching the metal-clad substrate at the ith processing        region, K_(i) to form electrically conductive patterns thereon;    -   (9) developing the i+1th photoresist layer section, P_(i+1);    -   (10) etching the metal-clad substrate at the i+1th processing        region, K_(i+1) to form electrically conductive patterns        thereon.

Referring to FIGS. 1-3, in step (1), the printed circuit board substrate100 is provided.

Referring to FIG. 4, in step (2), two orthogonal coordinate linespassing through the rotation center O shown as dash dot lines divide theprinted circuit board substrate 100 into four symmetrical processingregions, i.e., the first processing region 101, the second processingregion 102, the third processing region 103, and the fourth processingregion 104. The processing regions 101, 102, 103, and 104 correspond tothe circuit substrates 120 a, 120 b, 120 c, and 120 d respectively.

Referring to FIG. 5 and FIG. 6, in step (3), a photoresist layer 130 isapplied on the first electrically conductive layer 112 a of the firstmetal-clad substrate 110 a. The photoresist layer 130 includes fourphotoresist layer sections, i.e., the first photoresist layer section1301, the second photoresist layer section 1302, the third photoresistlayer section 1303, and the fourth photoresist layer section 1304. Thephotoresist layer sections 1301, 1302, 1303, and 1304 correspond to theprocessing regions 101, 102, 103, and 104 respectively.

Referring to FIGS. 7-9, in steps (4)-(6), a photo mask 200 having a sizesimilar to one processing region is provided, and the four photoresistlayer sections 1301, 1302, 1303, and 1304 are exposed by a light source(not shown) and the photo mask 200 in sequence. The photo mask 200 haspatterned openings 201 (as an example, three parallel openings 201 asshown in FIG. 7) to pass light (e.g. UV-light) through. The openings 201correspond to predetermined electrically conductive patterns which willbe formed in the first insulation layer 111 a using the firstelectrically conductive layer 112 a.

Firstly, referring to FIG. 8A, the photo mask 200 is aligned with thefirst photoresist layer section 1301.

Secondly, the first photoresist layer section 1301 is exposed to formpatterns corresponding to the openings 201.

Thirdly, referring to FIG. 8B, the printed circuit board substrate 100is rotated 90 degrees in a counterclockwise direction about the rotationcenter O of the first metal-clad substrate 110 a, so that the secondphotoresist layer section 1302 is aligned with the photo mask 200, andthe third circuit substrate 120 b is in the position the first circuitsubstrate 120 a was located before being rotated.

Additionally, precise adjusting of the photo mask 200 may be required toensure a precise alignment of the second photoresist layer section 1302and the photo mask 200.

Fourthly, the second photoresist layer section 1302 is exposed to formpatterns corresponding to the openings 201.

Fifthly, referring to FIG. 8C, the printed circuit board substrate 100is rotated 90 degrees again in a counterclockwise direction about therotation center O, so that the third photoresist layer section 1303 isaligned with the photo mask 200, and the third circuit substrate 120 cis in the position the second circuit substrate 120 b was located beforebeing rotated.

Sixthly, the third photoresist layer 1303 is exposed to form patternscorresponding to the openings 201.

Seventhly, referring to FIG. 8D, the printed circuit board substrate 100is rotated 90 degrees again about the rotation center O of the firstmetal-clad substrate 110 a, so that the fourth photoresist layer section1304 is aligned with the photo mask 200, and the fourth circuitsubstrate 120 d is in the position the third circuit substrate 120 c waslocated before being rotated.

Eighthly, the fourth photoresist layer section 1304 is exposed to formpatterns corresponding to the openings 201, thus the photoresist layer130 is completely exposed as shown in FIG. 9.

Referring to FIGS. 9-11, in steps (7)-(10), the photoresist layer 130 isdeveloped, the first electrically conductive layer 112 a is etched, andthe residual photoresist layer 130 is removed, therefore electricallyconductive patterns are formed on the first insulation layer 111 a usingthe first electrically conductive layer 112 a. In detail, theelectrically conductive patterns formed on the first insulation layer111 a include first electrically conductive patterns 1121 acorresponding to the first electrical traces 122 a, second electricallyconductive patterns 1122 a corresponding to the third electrical traces122 b, third electrically conductive patterns 1123 a corresponding tothe fifth electrical traces 122 c, and fourth electrically conductivepatterns 1124 a corresponding to the seventh electrical traces 122 d.

It is noted that the photoresist layer sections 1301, 1302, 1303, and1304 can be developed simultaneously, or can be developed in sequence.[0053] Furthermore, a plurality of vias can be formed in the printedcircuit board substrate 100 to interconnect the first electricallyconductive patterns 1121 a and the first electrical traces 122 a, thesecond electrically conductive patterns 1122 a and the third electricaltraces 122 b, the third electrically conductive patterns 1123 a and thefifth electrical traces 122 c, and the fourth electrically conductivepatterns 1124 a and the seventh electrical traces 122 d respectively.

Additionally, electrically conductive patterns are formed on the secondinsulation layer 111 b using the second electrically conductive layer112 b by similar processing steps as steps (3)-(10) described above.

Furthermore, a plurality of vias (not shown) can be formed in theprinted circuit board substrate 100 to interconnect the electricallyconductive patterns formed on the first insulation layer 111 a and thesecond insulation layer 111 b.

Referring to FIG. 12, the printed circuit board substrate 100 is cutalong imaginary boundary lines between the four processing regions toform four printed circuit board, i.e., a first printed circuit board 101a, a second printed circuit board 102 a, a third printed circuit board103 a, and a fourth printed circuit board 104 a. The first printedcircuit board 101 a corresponds to the first processing region 101 andhas the first circuit substrate 120 a attached thereon. The secondprinted circuit board 102 a corresponds to the second processing region102 and has the second circuit substrate 120 b attached thereon. Thethird printed circuit board 103 a corresponds to the third processingregion 103 and has the third circuit substrate 120 c attached thereon.The fourth printed circuit board 104 a corresponds to the fourthprocessing region 104 and has the fourth circuit substrate 120 dattached thereon.

Furthermore, coverlayers (not shown) can be covered on the printedcircuit boards 101 a, 102 a, 103 a, and 104 a to protect theelectrically conductive patterns formed on the first and secondinsulation layers 111 a, 111 b.

In the method, the four photoresist layer sections 1301, 1302, 1303, and1304 are exposed sequentially, therefore, if one of the photoresistlayer section is not aligned with the photo mask 200, the alignment ofother photoresist layer sections and the photo mask 200 would not beeffected. Thus, the yield rate of manufacturing a batch of printedcircuit boards is decreased compared to prior art manufacturing methods.In addition, by rotating the printed circuit board substrate 100, massproduction of the printed circuit boards can be achieved.

While certain embodiments have been described and exemplified above,various other embodiments will be apparent to those skilled in the artfrom the foregoing disclosure. The present disclosure is not limited tothe particular embodiments described and exemplified but is capable ofconsiderable variation and modification without departure from the scopeof the appended claims.

1. A printed circuit board substrate, comprising: a first metal-cladsubstrate; a number of N spaced circuit substrates arranged on the firstmetal-clad substrate along an imaginary circle, the circuit substratesbeing equiangularly arranged about the center of the circle, each of thecircuit substrates being oriented 360/N degrees with respect to aneighboring circuit substrate, N representing a natural number greaterthan
 2. 2. The printed circuit board substrate as claimed in claim 1,wherein the first metal-clad substrate includes a first insulation layerand a first electrically conductive layer formed thereon, the firstelectrically conductive layer is configured to form electricallyconductive patterns.
 3. The printed circuit board substrate as claimedin claim 2, wherein each of the circuit substrates has a secondinsulation layer and a plurality of electrical traces formed thereon,the electrical traces are in contact with the first insulation layer. 4.The printed circuit board substrate as claimed in claim 1, furthercomprising a second metal-clad substrate, the circuit substrates aresandwiched between the first and second metal-clad substrates.
 5. Theprinted circuit board substrate as claimed in claim 1, wherein N isequal to 4, and each of the circuit substrates is oriented 90 degreeswith respect to a neighboring circuit substrate.
 6. A circuit substrate,comprising: a first metal-clad substrate; a number of N spaced secondcircuit substrates arranged centrosymmetric with respect to a givenpoint on the metal-clad substrate, each of the circuit substrates beingoriented 360/N degrees with respect to a neighboring circuit substrate,N representing a natural number greater than
 2. 7. The printed circuitboard substrate as claimed in claim 6, wherein the first metal-cladsubstrate includes a first insulation layer and a first electricallyconductive layer formed thereon, the first electrically conductive layeris configured to form electrically conductive patterns.
 8. The printedcircuit board substrate as claimed in claim 7, wherein each of thecircuit substrates has a second insulation layer and a plurality ofelectrical traces formed thereon, the electrical traces are in contactwith the first insulation layer.
 9. The printed circuit board substrateas claimed in claim 6, further comprising a second metal-clad substrate,the circuit substrates are sandwiched between the first and secondmetal-clad substrates.
 10. The printed circuit board substrate asclaimed in claim 6, wherein N is equal to 4, and each of the circuitsubstrates is oriented 90 degrees with respect to a neighboring circuitsubstrate.